It is desired to continuously increase the memory density and to reduce the costs per bit in a memory cell arrangement. One approach to increase the memory density is to provide a memory cell arrangement having memory cells which are coupled with each other in accordance with a NAND coupling structure. Furthermore, the memory cells tend to be configured to store a plurality of bits in each memory cell.
In a conventional NAND memory cell arrangement, usually a threshold voltage of a memory cell is converted into one or more digital values (in general, e.g., into N digits) through hard decision, which one or more digital values are provided at a memory cell arrangement-external interface for further processing.
If more bits of information were available outside the memory cell arrangement, e.g., outside the NAND memory cell arrangement, by way of example, error correction code (ECC) and digital signal processing (DSP) elaboration can be used to recover, for example, memory cell intrinsic gain loss or memory cell intrinsic distribution shift. Furthermore, a wider spread of ECC algorithms could be used as with hard decision information.